1. Field of the Invention
This invention relates to a semiconductor device and a method of manufacturing same, and more particularly relates to a semiconductor device having an insulating film on a substrate and a method of manufacturing a semiconductor device having an insulating film on a substrate. Further, the present invention relates to a semiconductor device having an isolation region between cells and a method of manufacturing same, and more particularly to technology which is effective when applied to a semiconductor device having an isolation region between non-volatile memory cells which require high integration and a method of manufacturing same.
2. Description of the Related Art
High integration and increased storage capacity is being required for Electronically Erasable and Programmable Read Only Memories (EEPROMs). A non-volatile memory cell capable of storing data corresponding to the storage capacity of one bit of NAND type EEPROM is formed by a field effect transistor having a charge accumulation layer (a floating gate electrode). More specifically, a non-volatile memory cell includes a channel-forming region, a charge accumulation layer formed on the channel-forming region via a gate insulating film, a control electrode (a control gate electrode) formed on the charge accumulation layer via a gate insulating film, and source and drain regions.
In a memory cell array of a non-volatile memory device, a data line and a word line intersect with each other. A plurality of non-volatile memory cells, such as 8 memory cells, for example, have a common source region and a common drain region (These plural non-volatile memory cells are connecting with each other and are arranged in a sequence along the extending direction of the data line. These plural non-voltage memory cells form one byte. A non-volatile memory cell located at one end of the sequence is connected with the data line through a select gate and a non-volatile memory cell located at the other end of the sequence is connected with the source line directly or through a select gate. A control electrode of each of the plurality of cells is connected with each word line.
Information “0” or “1” is stored in a non-volatile memory cell depending on whether or not a charge (electron) is accumulated in the charge accumulation layer. In accordance with the information stored, whether or not a current flows between the source and drain regions is determined.
In order to achieve high integration and increased memory capacity of a NAND type EEPROM, it is significant to minimize the size of non-volatile memory cells. Here, it is inevitable to decrease the area of an isolation region between non-volatile memory cells which are adjacent to each other. Japanese Patent Laid-Open Publication No. 2005-243709 discloses a semiconductor device in which the area of the isolation region can be decreased by means of a combination of shallow trench isolation (STI) technique and film forming technique and a method of manufacturing the same.
Specifically, in the semiconductor device and the method of manufacturing the same disclosed in Japanese Patent Laid-Open Publication No. 2005-243709, the shallow trench isolation technique is employed to form a trench in a semiconductor substrate, and a silicon oxide film is buried within the trench. As this silicon oxide film, a silicon oxide film formed by High Density Plasma-Chemical Vapor Deposition (HDP-CVD) method and a silicon film which is coated by Spin On Glass method and converted and layered on the silicon film previously formed are employed.
In the semiconductor device and the method of manufacturing the same disclosed in Japanese Patent Laid-Open Publication No. 2005-243709, as an interval between adjacent non-volatile memory cells of a non-volatile memory device can be secured in the depth direction of a semiconductor substrate by means of the trench, the area of the isolation region can be decreased. Further, the silicon oxide film formed by HDP-CVD method has a dense film quality, and therefore has excellent resistance to leakage current. On the other hand, the silicon oxide film formed by spin-on-glass method has flowability when it is coated, and can therefore fill the interior of the trench to a sufficient degree even when the size of an opening of the trench is small. In particular, the former silicon oxide film is buried within the trench and simultaneously is formed so as to cover the surface of a charge accumulation layer of the non-volatile memory cell, whereby charge storage characteristics can be enhanced. Further, in the manufacturing process of a non-volatile memory device, a mask which is used for patterning the charge accumulation layer of a non-volatile memory cell is used for forming the trench, and therefore the aspect ratio between the height from the mask surface to the bottom of the trench and the size of the opening of the trench is large, so that the latter silicon oxide film can reliably fill the interior of the trench.
With the semiconductor device and the method of manufacturing the same as described above, however, no consideration has been taken concerning film separation and generation of cracks which occurs at an interface between the silicon oxide film having dense film quality formed by HDP-CVD method and the silicon oxide film formed by spin-on-glass method, resulting from film densities of these silicon oxide films.